Full flow for transistor simulation based on edge-contour extraction and advanced SPICE simulation

Abstract

A methodology for predicting on and off-state transistor performance is described in this paper. In general, this flow consists of systematic Edge-Contour-Extraction (ECE) from devices under the manufacturing, followed by device simulation. Gate parameter extraction calculates an equivalent gate length and width (L eq , W eq ) for non-rectangular gates. The methodology requires a model describing MOSFET behavior of current versus width for various gate lengths and voltages. Non-rectangular gates are described by a weighted sum of the currents from a discrete representation (i.e. Total gate current is determined by a weighted sum since the current distribution is not homogeneous along the channel). Thus, for a given L, W and V, the current should be discoverable from the calibrated model. This approach is more general than previous work as both L eq and W eq are determined for a given voltage which permits the model to predict on and off-current with a single spice netlist as opposed to previous work which only considered adjustments to the channel length. In this work, two transistor series at two different drawn pitch conditions (dense and isolated) were manufactured, followed by state-of-the-art ECE. The contours obtained directly by SEM measurements were used to perform an electrical device simulation for each individual transistor in the series. This paper demonstrates the possibility to analyze the transistor's electrical performance at nominal and off-process conditions. The presented simulation flow provides the advantage of early-in-time prediction of the transistor performances, measuring large volume of devices in a fast and accurate fashion.