Abstract
This paper proposes 1 bit full adder using double-gate FinFet transistor and Gate Diffusion Input (GDI) technique. Using GDI cell makes it possible to reduce the number of transistors and merging this technique with double gate process causes further reduction in power and delay. Although, double gate transistors with independent gates are the choice for low power design, we use both dependent and independent gates in proposed circuit to achieve lower power. This issue is related to GDI cell properties which is discussed in more details in this paper. Simulations are performed on 45nm providing a sub-circuit model for FinFET from PTM and 1V supply voltage. According to our simulation result, the proposed full adder is better than prior designs in terms of power and power*delay.
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