Fulfillment of Some Important Voltage Harmonic Standards in a FPGA Controlled CHB Multilevel Inverter Utilizing Improved SHM-PAM Technique

Abstract

In the area of medium voltage and high power multilevel inverter applications, good quality power output can be achieved by minimizing lower-order harmonic components, and the SHM-PAM scheme produces best results in this context. The minimization of selective lower-order harmonics rather than their complete elimination makes it more useful to comply certain grid code standard. This article proposes an improved SHM-PAM scheme for a 3-phase 7-level CHB-MLI utilizing three new half-wave (HW) symmetry waveforms to comply with six well-known grid code standards, namely CIGRE WG 36-05, EN 50160, NRS 048-2, IEC 61000-2-12, IEC 61000-3-6, and ER G5/4. The optimal switching transients and necessary dc-link voltages have been determined for controlling the CHB MLI using the recently reported dragonfly algorithm (DA). The efficacy of the reported scheme is evaluated satisfactorily by simulation study and hardware investigation on a CHB-MLI laboratory prototype. The power loss analysis of the CHB inverter for the proposed schemes is evaluated for the entire power factor range. Additionally, to demonstrate the suggested method's superiority in terms of necessary commutation angles for grid code fulfilment, a comparative study has been carried out with a number of pre-existing modulation-schemes.