Abstract

This paper presents an overview of the ATLAS Fast TracKer (FTK) processor, reporting the design of the system, its expected performance, and the current integration status. The FTK is an upgrade of the trigger system of the ATLAS experiment. The system is designed to reduce the event rate from the proton-proton collisions occurring at 40 MHz to about 1 kHz for the expected LHC luminosity (2 × 1034 cm−2s−1). To achieve this selection rate, the FTK system must exploit an intensive use of particle tracking. To this purpose, a dedicated hardware tracker has been designed: the FTK processor. To achieve the required performance, FTK uses a combination of custom VLSI chips and latest generation FPGAs, all embedded in dedicated boards, and it exploits a fully parallel architecture. FTK provides track reconstruction based on the full silicon (inner) detector with resolution comparable to the offline reconstruction with a latency of approximately 100 μs.

Highlights

  • Fast TracKer (FTK) is an electronic system able to find and reconstruct particle trajectories from the inner detector of ATLAS [1],[2]

  • As data are transmitted from the Read Out Drivers (ROD) according to the level-1 trigger rate, FTK receives input silicon data at full rate and high bandwidth

  • The system works in two stages: (1) 8 of 12 silicon detector layers are used to perform pattern recognition and to obtain an initial fitting; (2) the found tracks are refined and output data are formatted to be compatible with the ATLAS protocols for the level-2 trigger system

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Summary

INTRODUCTION

FTK is an electronic system able to find and reconstruct particle trajectories (tracks) from the inner detector of ATLAS [1],[2]. It rebuilds the track information by looking at 12 logical layers 4 pixel layers including the new Insertable BLayer (IBL)[3]; 8 Silicon Microstrip Trackers (SCT) layers corresponding to the axial and stereo sides of 4 physical layers. Dual-output High-speed Optical Link (HOLA) has been installed by replacing the existing HOLA output mezzanine cards in the pixel and SCT Read Out Drivers (ROD). The two copies of data are given in parallel to the FTK processor and to the Read Out System (ROS). At a luminosity of 3 × 1034 cm−2s−1 the handling of huge amount of data is an important design challenge

FTK ARCHITECTURE
CURRENT STATUS
EXPECTED PERFORMANCE
Findings
CONCLUSION
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