Ft of 100GHz for 100nm multi-gate In<inf>0.53</inf>Ga<inf>0.45</inf>As MOSFET

Abstract

In this paper, multi-gate In 0.53 Ga 0.47 As MOSFETs were fabricated with different numbers of gate-fingers (4, 8, and 16) using air-bridge technology. The gate oxide of 8nm Al 2 O 3 was deposited by ALD (Atomic Layer Deposition). The device was fabricated by self-aligned method with the gate deposition at first. For MOSFET with the gate length of 100nm, we achieved a maximum drain current Id of 120mA/mm, and a maximum extrinsic transconductance gm EXT of 75mS/mm at room temperature. A cut-off frequency of 100GHz and a maximum oscillation frequency of 31GHz were obtained with 16 gate-fingers. A further intrinsic transconductance gm INT of 550mS/mm was obtained by S-parameter measurements, which is several times higher than that of the DC value. This increase is attributed to the reduction of the interface traps response at the oxide semiconductor interface at high frequency. III-V materials are doing well in recent decades due to their exceptional properties like higher mobility, higher saturation velocity, and narrow band gap…compared to their counterparts Si. With the feasibility of obtaining high quality dielectric insulating layer on III-V materials by different deposition methods and various surface treatments, it is possible to fabricate III-V MOSFET for high frequency applications with low power dissipation. In this paper, multi-gate In 0.53 Ga 0.47 As MOSFETs were fabricated with Al 2 O 3 as gate oxide deposited by Atomic Layer Deposition. Details of the gate-first process flow can be founded in ref.[1]. Tantalum metal was used for the realization of the gate. This metal gives huge gate resistance, which avoids the extraction of accurate small signal equivalent circuit. To overcome this problem, we realize multi-gate topology. Fig. 1 shows the SEM image of In 0.53 Ga 0.47 As MOSFETs with 8 gate fingers obtained with the process flow listed. The DC and RF measurements were carried out at room temperature. Fig. 2, 3 give the DC characteristics of the device. A maximum drain current of 120mA/mm, and a maximum extrinsic transconductance of 75mS/mm were obtained. These values are extremely low compared with published results, with gm EXT and Id of about 1S/mm and 1A/mm respectively [2, 3]. By extrapolation of extrinsic current gain and Unilateral Masons's gain from S-parameter measurements, a cut-off frequency f T of 100GHz, and a maximum oscillation frequency f MAX of 31GHz were obtained (Fig. 4). Tantalum metal gate gives high gate resistance, which limits the f MAX . Despite a weak gm EXT , which is one order lower than reported values, f T reaches 100GHz. We attribute this behaviour to the frequency dispersion of charge command. Indeed at low frequency, the inversion charges are screened by interface traps, which limit the transconductance. A C-V measurement was carried out, and large frequency dispersion was observed. Using HF-LF method, an interface trap density Dit of 3∗1012/cm2 eV was extraxted (Fig. 5). This large Dit contributes to the low gm EXT . At high frequency this behaviour should disappear since the traps who have relatively long relaxation time don't have enough time to react, thus transconductance should be higher. To confirm this hypothesis, we extract the small signal equivalent circuit. Values are reported in Table 1, for a total width of 8∗15μm (8 gate fingers) at gate bias corresponding to the maximum transconductance and V ds =1V. These values were extracted above frequency, where elements were independent of frequency. gm INT is 542mS/mm, which is almost one order magnitude higher than gm EXT . Contribution of source resistance R S to the extrinsic transconductance gives calculated gm EXT equal to 506mS/mm, which is still 7 times higher than the measured gm EXT . Thus, the large discrepancy of DC and intrinsic transconductance is attributed to interface traps.