FSM dual logic synthesis targeting area optimization

Abstract

To cope with the problem that exiting in the area optimization of the finite state machine(FSM) by only using traditional Boolean logic operations, a novel algorithm for FSM area optimization using both traditional Boolean logic and Reed-Muller logic, namely dual logic, is proposed. By introducing the majority cover of a logic function, and defining the coefficient of the majority cover and the remainder of the majority cover, a cost function of the FSM area is presented which helps the genetic algorithm to finish state assignment for the FSM dual logic synthesis. The proposed algorithm has been implemented in C and tested under the MCNC benchmarks. The experimental results show that for most 76% test cases, the proposed dual logic optimization algorithm can reduce FSM area further in contrast to the method which only employs traditional Boolean logic.