FSM-based formal compliance verification of interface protocols

Abstract

of the important steps in a platform-based system-on-a-chip design methodology. There are limitations for most of the existing methods for interface protocol compliance verifi- cation. Simulation-based methods have the false positive problem while formal property checking methods may suffer from memory explosion and excessive runtime. In this pa- per, we propose a novel approach for interface protocol compliance verification. The properties of the interface protocol are first specified as a specification FSM. Then the compliance of interface logic is formally verified at the higher FSM level so that the re- quired memory and runtime can be greatly reduced. Finally, it is shown theoretically and experimentally that the proposed algorithm possesses acceptably low time complexity for practical applications.