Abstract
We report on the design and performance of an ASIC named FSDR16 dedicated for readout of silicon strip detectors. The FSDR16 chip contains 16 channels with the size of 60µm × 880µm. Each channel contains a charge sensitive amplifier, a pole-zero cancellation circuit, a 5th order complex pulse shaping amplifier stage based on a follow-the-leader filter architecture, 7-bit trim DAC for offset correction and 8-bit shift register. The designed readout front-end system characterizes low power dissipation P = 2.5mW per single channel. The peaking time t p of the shaper is set to 100 ns or 200 ns. The complex shaper architecture allows to obtain a shorter pulse width (the pulse width to peaking time is only t 0.01 /t p = 2.86) than in the case of standard CR-(RC)5 (t 0.01 /t p = 3.46) filter, and to operate with a higher rate of input pulses. Equivalent Noise Charge of the front-end channel is equal to 254e− rms for t p = 100 ns and 184e− rms for t p = 200 ns.
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