From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration

Abstract

As CMOS technology continues to scale down due to advances in lithography, the interaction of neighboring patterns is exacerbated. Every pattern printed on silicon is influenced by its neighbors given a technology-specific interaction range. As transistors and cells shrink to sizes of the same order of the interaction range, pattern dependencies at the 16-nm node (and below) make the prediction of functional and parametric yield challenging. Precharacterizing all combinations of layouts as a function of all possible neighboring patterns is impractical due to exponential complexity, whereas silicon characterization of all patterns is practically impossible. In this paper, we propose a virtual characterization vehicle (VCV) methodology that can exhaustively identify all uniquely occurring layout patterns in a standard cell library. VCVs can expose all cell neighboring arrangements as a function of a radius of influence while compiling the pattern frequency and also uncovering the arrangement of cells that create unique patterns. Effects that span multiple layers are also captured in our analysis. VCV results can be used to co-design libraries by suggesting favorable compositions as well as favorable layout styles. Finally, VCVs can be turned into test-chips that are guaranteed to cover all identified patterns with the aid of self-testing features. An extremely regular library was developed in 16-nm FinFET technology and is used to showcase our pattern analysis in which DFM quality is shown to be improved with respect to commercial libraries. Our silicon results demonstrate the feasibility of turning the VCV approach into real silicon test chips.