Abstract
This work aims to automatically generate process controllers' VHDL implementation code amenable to be deployed into a platform integrating graphical synoptic updating. These controllers will be implemented on FPGA based reconfigurable platforms, incorporating dedicated graphical interfaces and input/output interfaces allowing its physical connection to the process under control. The system controller behavior is modeled using IOPT Petri Nets models. A tool called Animator4FPGA was developed, which achieved this goal in cooperation with other tools developed within FORDESIGN project, namely an IOPT Petri nets graphical editor, the Animator tool, and an automatic code generation tool from Petri nets to VHDL code.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
