From chip to inverter: Electro-thermal modeling and design for paralleled power devices in high power application

Abstract

Power loss and thermal stress of semiconductor components are closely related to the reliability of high power inverter. In addition to the inverter electrical parameters, the size of semiconductor is also an important factor in inverter electro-thermal performance. In this paper, an electro-thermal model correlated with chip area and chip paralleled number is built to calculate the power switch loss and junction temperature. Then, the relationship between chips size and inverter loss/thermal behaviors can be established by this model, enabling more flexible in chip design to optimize the inverter efficiency and thermal loading. Finally, the inverter electro-thermal design procedure is established to properly select the chip area and number in a power switch. As a case study, the optimal chip paralleled structure in the high power inverter is estimated and the results are compared under varying inverter output frequency. By selecting the chip area and number in the target region, junction temperature can maintain in the limited range.