From 32 nm to TFET Technology: New Perspectives for Ultra-Scaled RF-DC Multiplier Circuits

Lionel Trojman,Eduardo Holguin,Marco Villegas,Ramiro Taco,Luis-Miguel Procel

doi:10.3390/electronics11040525

Lionel Trojman, Eduardo Holguin + Show 3 more

Open Access

https://doi.org/10.3390/electronics11040525

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Abstract

In this present work, different Cross-Coupled Differential Drive (CCDD) CMOS bridge rectifiers are designed using either 32 nm or Tunnel-FET (TFET) technology. Commercial PDK has been used for the 32 nm technology, while lookup tables (LUT) resulting from a physics model have been applied for the TFET. To consider the parasitic effects for the circuit performances, the 32 nm-based circuits have been laid out, while a parasitic model has been included in the TFET LUT for circuit implementation. In this work, the post-layout simulations, including parasitic, demonstrate for conventional CCDD circuits that TFET technology has a larger dynamic range (DR) (>60%) and better 1 V-sensitivity than the 32 nm planar technology has. Note that, in this case, the figure of merit defined by the Voltage Conversion Efficiency (VCE) and Power Conversion Efficiency (PCE) remains somewhat similar. On the other hand, topology proposing better VCE at the cost of low PCE shows lower performance than expected in 32 nm than in reported data for larger technology nodes (e.g., 180 nm). The TFET-based circuit shows a PCE of 70%, VCE of 82% with an 8 dB DR (>60%), and the best 1 V-sensitivity in this work. Because of the low-bias condition and the good reverse current blocking (unidirectional channel), the TFET offers new perspectives for RF-DC rectifier/multiplier topology, which are usually limited with planar technology.

Highlights

Such system integration is made possible by applying the System-on-Chip (SoC) strategy which is essentially employed for smart object conception
Note that that the the results results are are benchmarked benchmarked with the ones provided with the ones provided by the by the circuit simulation of the conventional Cross-Coupled Differential Drive (CCDD) labelled as CDC (Figure 3a) [13]
Conventional and based CCDD circuit topologies have been considered to implement multipliers for Radio Frequency Energy Harvesting (RFEH) systems. These circuits have been optimized for the 32 nm planar and TFET nonplanar technologies by including the parasitic effect, resulting in a layout implementation

Summary

Introduction

The Internet of Things (IoT) requires more and more compact systems, resulting in the integration of the same monolithic chip (generally) sensors, memory, microprocessor, BT port, and power supply blocks Such system integration is made possible by applying the System-on-Chip (SoC) strategy which is essentially employed for smart object conception. IoTs or smart objects are part of an important electronic market motivated by the relatively new Moore than More (MtM) paradigm [1] Many applications, such as RFID wireless sensors for biomedical devices have allowed extensive research on a specific rectifier: the RF-DC power converter. Engineers have concentrated their efforts on the possibility of wireless IoT implementation, namely independent of a centralized power source To reach this goal, the concept of harvesting energy has been recently introduced to empower the electronic system [2]. The rectifier or RF-DC converter provides a micropower DC signal to a Power Management

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