Frequency‐to‐voltage converter based dual‐loop phase‐locked loop with variable phase locking capability

Abstract

A novel frequency-to-voltage converter based phase-locked loop (PLL) is proposed to overcome the inability of a frequency-to-voltage converter based frequency-locked loop to lock phase. The proposed dual-loop PLL adds variable phase-locking capability, such that the phase locking angle can vary from 0–360°. The additional variable phase-locking can be applied in data communication in the form of phase modulation. The design is targeted for a 0.5-μm CMOS process. The proposed design generates a 480 MHz clock from a reference clock of 15 MHz. In simulation, the proposed PLL locks within 3.56 μs while consuming 1.61 mW of power.