Frequency-range enhanced delay locked loop based on varactor-loaded and current-controlled delay elements

Abstract

In this paper, some building blocks of the conventional delay-locked-loops are modified to achieve a higher frequency range and smaller jitter on generated phases. A novel sensitive and dead-zone free phase detector is proposed with a reduced number of MOS transistors. A voltage-controlled capacitive load is added to the basic delay elements to expand the lower limit of the locking frequency range from 50 MHz to 10 MHz. Besides, the upper limit of the operating frequency is improved from 1 GHz to 1.5 GHz, by reducing the input capacitance of the delay cells via an auxiliary shortening path. Rigorous theoretical analysis is provided on the capacitance variations and the expanded frequency range. Post-layout simulation results confirm that RMS and peak-to-peak jitter of 0.83 pS and 6.85 pS are achieved at 1 GHz operating frequency when 1.8 V supply is subject to random noise components with peak-to-peak variations of 66 mV. The proposed strategy consumes the maximum power of 6.3 mW at TT conditions, within the frequency range of 10 MHz-to-1.5 GHz, and occupies 0.0036 µm2 active area. Simulation results are presented using the BSim3v3 model of MOS transistors in a 0.18 µm CMOS process.