Abstract
A new frequency multiply circuit generating a 20 GHz sampling clock from an external 5 GHz signal for a lowpass sigma-delta modulator was proposed and designed. The multiply circuit was composed of a ladder circuit, a modified Josephson transmission line (JTL) and T-flip flop (T-FF). We confirmed by numerical simulation that the period jitter of SFQ pulse trains generated by the ladder circuit could be reduced to a value small enough to realize 14-bit resolution for 10 MHz bandwidth by utilizing the repulsion effect between SFQ pulses in the modified JTL. The multiply circuit was fabricated by a 2.5 kA/cm/sup 2/ Nb process, and its correct operation was confirmed.
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