Abstract
This paper discusses a hardware-assisted IEEE-1588 implementation with direct control of the processor clock. IEEE-1588 is a new standard, used for clock/time synchronization in packet-based networks. A comparison between hardware vs. software-oriented implementations is also discussed, including the general pros and cons of the two methods. The target of the present implementation is homogenous Ethernet local area networks with applications in control systems, automation, test and instrumentation as well as telecommunications. The proposed architecture was tested and experimented into an Altera® FPGA (Field Programmable Gate Array) and we believe it represents a simpler and more precise implementation of the IEEE-1588 standard.
Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
