Abstract
Using application-specific instructions for heterogeneous multiprocessor system-on-chip (Ht-MPSoC) allows to find a good performance/energy trade-off. For MPSoC architecture executing different multimedia applications, we expect a large number of potential custom instructions. In order to explore the potential of all these instructions, we propose to identify the similar critical computations to be executed on hardware accelerators (HWA) shared between processors. Depending on the running applications in one side and their needs in performance and area usage on the other side, private and shared hardware accelerators are attached to the different cores. This leads to a large architectural space exploration. In this letter we propose an FPGA-based framework capable of identifying the configuration of HWA targeted to an MPSoC architecture. Our framework incorporates a hardware accelerators sharing methodology to optimize area/performance tradeoff. The comparison of framework-estimated results and real measurements proves the efficiency of our framework.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
