Framed bit error rate testing for 100G Ethernet equipment

Abstract

The Internet users behavioural patterns are migrating towards bandwidth-intensive applications, which require a corresponding capacity extension. The emerging 100 Gigabit Ethernet (GE) technology is a promising candidate for providing a ten-fold increase of todays available Internet transmission rate. As the need for 100 Gigabit Ethernet equipment rises, so does the need for equipment, which can properly test these systems during development, deployment and use. This paper presents early results from a work-in-progress academia-industry collaboration project and elaborates on the challenges of performing bit error rate testing at 100Gbps. In particular, we show how Bit Error Rate Testing (BERT) can be performed over an aggregated 100G Attachment Unit Interface (CAUI) by encapsulating the test data in Ethernet frames at line speed. Our results show that framed bit error rate testing can be performed at speeds exceeding 100Gbps using commercially available Field Programmable Gate Arrays (FPGAs). Even though extensive parallelization is used to achieve this goal, the resulting resource consumption of the proposed design remains relatively modest, leaving plenty of room for additional functionality besides the bit error rate tester.