Fractional-N DPLL-Based Low-Power Clocking Architecture for 1–14 Gb/s Multi-Standard Transmitter

Abstract

A low-power clocking solution is presented based on fractional-N highly digital LC-phase-locked loop (PLL) and sub-sampled ring PLL targeting multi-standard SerDes applications. The shared fractional-N digital LC-PLL covers 7–10 GHz frequency range consuming only 8-mW power and occupying 0.15 mm2 of silicon area with integrated jitter of 264 fs. Frequency resolution of the LC-PLL is 2 MHz. Per lane clock is generated using wide bandwidth ring PLL covering 800 MHz to 4 GHz to support the data rates between 1 and 14 Gb/s. The ring PLL supports dither-less fractional resolution of 250 MHz, corrects I/Q error with split tuning, and achieves less than 400-fs integrated jitter. Transmitter works at 14 Gb/s with power efficiency of 0.80 pJ/bit.