Fractional charge packet counting with constant relative resolution

Abstract

SUMMARYA charge‐to‐digital converter concept suitable for pixel‐level charge sensitive amplifiers is presented. The circuit implements a technique referred here as fractional charge packet counting, which ensures large dynamic range operation using constant integration time. By means of a particular circuit arrangement a constant number of significant bits is provided as output, thus ensuring a constant relative resolution over the entire dynamic range.A circuit implementing the concepts described above has been designed and simulated. Each block of the circuit is described in details and its characterization is presented. The circuit is capable to convert input currents in the range of 100 fA to 100 nA at 2 ksample/s with a constant resolution of 10 bit without the need of gain switching. Copyright © 2010 John Wiley & Sons, Ltd.