FPLD implementation of a PN-matched filter correlator

Abstract

Typical spread-spectrum receivers use a sliding correlator to achieve synchronization with a received direct sequence spread spectrum (DSSS) signal. A faster approach (lower latency) to synchronization that uses much shorter synchronization preambles is to use a parallel or tapped delay line correlator to implement a pseudorandom noise (PN) matched filter. Surface acoustic wave (SAW) devices, charge coupled devices (CCD) and digital signal processing (DSP) components are commonly used to implement PN-matched filters. An analysis of a tapped delay line implementation of a PN-matched filter using field programmable logic devices (FPLD) is presented. A pipelined architecture is used to accelerate the calculations and improve the speed of the matched filter. The analysis and simulations show that using standard FPLDs a 16-chip PN-matched filter with a 4-bit, soft-decision input can be implemented with a sampling rate in excess of 100 MHz. If 2X over sampling is used in the absence of chip synchronization, this translates to a chip rate over 50 Mcps and a data rate in excess of 3 Mbps. Therefore, this filter is feasible and even advantageous for moderate speed wireless networks, particularly those with small packet lengths or requiring low latency.