Abstract

This paper presents the design methodology of a complete digital pre-distortion system that enables the power amplifier linearization. This system employs the memory polynomial model for its realization. The performance of the linearization is validated by using an LTE carrier signal in the band of 10 MHz. This integrated solution is capable of linearizing any real power amplifier from measurements of AM/AM and AM/PM conversion curves. Furthermore, this development test bed is able to predict the behavior and facilitates the design analysis of a pre-distorter. The experimental results are implemented employing a DSP-FPGA by using DSP Builder tool to obtain the VHDL hardware description. The proposed model shows a spurious-free dynamic range of 50 dBm and an adjacent channel power ratio reduction of 25 dBc for the NXP 10W power amplifier.

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