FPGA-Based Implementation of Discrete Fractional Fourier Transform Algorithm

Abstract

Fractional Fourier transform (FrFT) has been taken a considerable attention in signal and image processing domain. On the evolution of discrete form of FrFT, low computational complexity is essential in practical applications. We proposed an efficient field programmable gate array (FPGA) implementation method for FrFT algorithm. The proposed architecture decomposes the calculation process of FRFT into one convolution and two multiplications to simplify the computational complexity. Additionally, we adopt a sinc interpolation as an interpolation algorithm to improve the accuracy of interpolation, and the finite impulse response filters are used to form a convolution module, which improves the robustness of signal convolution. The proposed architecture has been synthesized with simulink and verilog hardware description language (HDL), targeting a FPGA device (XC7VX690T). The obtained results are very close to the simulation results. Finally, architectural design and hardware requirements along with constituent blocks in architecture are discussed.