FPGA-based Implementation of a Correlator for Kasami Sequences

Abstract

Kasami sequences have been successfully used in communications, navigation and related systems due to their low cross-correlation values, compared to those from other binary sequences. In this work, different alternatives for the hardware implementation of a correlator of Kasami sequences are presented: for short sequences a combinational design is proposed, whereas three sequential designs are suggested for longer Kasami sequences. These three sequential designs differ about the management of the memory: one stores the necessary data in slices of the FPGA; another uses external memory; and finally, the last one uses the internal RAM blocks in the FPGA.