FPGA-based accelerator platform for big data matrix processing

Abstract

Big data analytics requires to analyze data at the rate that matches the speed of data production. Therefore, some software frameworks such as Hadoop with high scalability and fault tolerance had been proposed to enable massive data storage and processing over large clusters of computing servers. However, the performance of data analytics can be further improved by deploying hardware accelerators to the computing servers. In this paper, an FPGA-based hardware accelerator platform for big data matrix processing is presented. The proposed accelerator platform is composed of many FPGA evaluation boards (EVBs). The computing server communicates with FPGA EVBs with Gigabit Ethernet. In addition, the FPGA can be reprogrammed for different data processing operations with high flexibility. The experimental results for one hundred 512×512 floating point matrix multiplications show that the proposed hardware accelerator platform with four FPGA EVBs at 125MHz clock rate can achieve the 4x speedup as compared with the computing server with an Intel I7-4770 CPU at 3.4GHz.