FPGA static timing analysis enhancement based on real operating conditions

Abstract

FPGAs are very sensitive to their operating conditions which can induce runtime errors. To prevent timing errors, FPGA manufacturers propose static timing analysis tools to ensure that the application to be implemented in the FPGA will work correctly at the expected frequency. However, that static timing analysis is corner-based and is thus valid for a set of optimal or recommended operating conditions. In the same time, the real operating conditions can be outside these corners when the FPGA is used in a harsh environment. In this paper, we propose a static timing analysis enhancement technique based on the real operating conditions that the FPGA will encounter. Thus, the static timing analysis can be done outside the predefined corners to ensure that the FPGA application will execute correctly in the real operating conditions. We also present some results showing the accuracy of our method and its application to an automotive application intended to be deployed in an aggressive environment.