FPGA Resource Requirements for Thermistor Linearization: A Comparative Study

Abstract

In this paper, five popular linearization techniques, namely, look up table (LUT), piecewise linearization (PWL), polynomial interpolation (PLI), artificial neural network (ANN) and adaptive neuro-fuzzy inference system (ANFIS) have been investigated on field programmable gate arrays (FPGA) for thermistor linearization. Relative FPGA resource requirements are evaluated for a given linearization accuracy assessed in terms of mean square error (MSE) and mean absolute deviation (MAD) values. Experimental validations, on FPGA in LabVIEW environment, performed for an MSE of ~10−5 have demonstrated that LUT requires minimum resources, PWL and PLI consume moderate resources, and ANN and ANFIS maximum resources. The other major contribution of this work has been in identifying the settings of trade-off parameters for all the above five techniques to obtain a given MSE. Presented results are expected to enable instrumentation engineers to select the suitable technique and tune its trade-off parameters for their applications based on the available FPGA resources.