FPGA Resource Efficient M-PSK Detector for Large MIMO and Multiuser Systems

Abstract

An M-ary PSK detector, named multiple-phase detector (MPD), is presented that is efficient for both MIMO and multiuser detection, particularly when the number of transmit antennas/users is high. The detector is based on a novel iterative phase descent search (PDS) algorithm. The PDS algorithm arrives at a solution using coordinate descent iterations, where coordinates are the unknown symbol phases, and the solution is constrained to a unit magnitude. In the MPD, the PDS is used multiple times with different initializations; the solution with the minimum cost is then chosen as the final MPD solution. Numerical results show that in a variety of scenarios the MPD performance is close to the optimal performance, whereas its complexity is lower than that of advanced techniques. We present a hardware architecture and FPGA implementation of the MPD. The proposed architecture maximizes the processing speed and minimizes the programmable logic resources. The proposed design requires as few as about $$330$$330 Xilinx logic slices for $$32\times {32}$$32×32 and $$64\times {64}$$64×64 MIMO systems and supports a speed of 450 MHz. The fixed-point implementation demonstrates a detection performance which is very close to the performance of the floating point counterpart.