FPGA real time synthesis of simplified SIFT algorithm

Abstract

This work presents an all-hardware real time implementation of the SIFT algorithm. The implementation exploits pipeline structures both in the keypoint extraction and in the descriptor generation stages to achieve real time requirements. To allow a feasible hardware implementations, some simplifications to the original algorithm have been required. The architecture has been synthesized on a Xilinx FPGA. It generates 3072 descriptor vectors for VGA images at 99 frames per second.