FPGA PROTOTYPING OF CONFIGURABLE SAMPLING RATE CONVERTER FOR SOFTWARE DEFINED RADIO (CSR-SDR) USING CIC FILTER

Abstract

A Software Defined Radio (SDR) system is a radio communication system, which uses software for modulation and demodulation of radio signals. In software defined radio (SDR) receivers, high-precision clock with very low jitter is required. It is intuitive to use only one fixed master clock. However, different wireless standards use different master clock rates. Under such circumstances, digital sample rate conversion (SRC) can be used as an important solution to provide different clock rates. The basic methods used in the SRC technology are decimation with down-sampling and interpolation with up-sampling, Down-sampling has to be preceded by filtering in order to avoid aliasing, while up-sampling must be followed by filtering to reject spectral images. In this paper, the design was implemented in FPGA using Verilog. The sampling rate conversion is performed by sampling the incoming signal and interpolating/decimating the signal to the desired value and then applying the low pass filter to eliminate aliasing. The sampling is done by digital mixer (Numerical controlled oscillator). The Interpolation/Decimation is performed by the CIC filter. FIR filter performs the low-pass filtering. The sampling rate converted value is given to the DSP processor for further processing. The projected application of the CSR_SDR are in GSM handset, CDMA handset and all the wireless applications. In this paper the functionality has been implemented, verified and checked using Verilog.