FPGA placement optimization methodology survey

Abstract

Field programmable gate array (FPGA) is a programmable chip that can be used to quickly implement any digital circuits. Placement is an important part of FPGA design step which determines physical arrangement of the logic blocks in the FPGA. The quality of placement of logic blocks determines overall performance of the logic implemented in the FPGA. In this paper, a number of placement optimization techniques are reviewed; min-cut, quadratic, simulated annealing, and a hybrid approach of using genetic algorithm with simulated annealing technique. The methodology of each optimization technique is presented and its advantages and disadvantages are evaluated. Overall, the hybrid approach of using genetic algorithm with simulated annealing technique produces best result, reaching a global optimal solution. The hybrid approach of using genetic algorithm and simulated annealing optimization technique is implemented using MATLAB and its results are presented using a wire-length-driven placement as cost function.