FPGA Implementations of Espresso Stream Cipher

Abstract

Security of resource-constrained hardware devices, such as the devices in Internet of Things regime, must consider performance and area consumption metrics. One of the viable options for designing lightweight cryptography could be stream cipher. The stream ciphers are symmetric ciphers designed for resource-limited devices. In this paper, we implemented the Espresso stream cipher on the Xilinx Spartan-7 FPGA device. During our implementation, we considered four cases: basic implementation with a full-width input, serial implementation with an unpipelined (basic) algorithm, serial implementation with a pipelined algorithm, and parallel cases. According to the results received, the parallel version reached a throughput of 1778 Mbps and consumed 113 slices. The serial version with an unpipelined output had the least area consumption of 68 slices to achieve a throughput of 511 Mbps. Results of implemented design are then compared with other stream cipher implementations, namely, Grain, Trivium, and MICKEY. It is identified that, despite limited parallelization, the Espresso stream cipher has one of the lowest area consumption compared to other stream cipher implementations.