FPGA Implementation of the Range-Doppler Algorithm for Real-Time Synthetic Aperture Radar Imaging

Yeongung Choi,Yunho Jung,Myeongjin Lee,Dongmin Jeong,Wookyung Lee

doi:10.3390/electronics10172133

Yeongung Choi, Yunho Jung + Show 3 more

Open Access

https://doi.org/10.3390/electronics10172133

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Journal: Electronics	Publication Date: Sep 2, 2021
Citations: 8	License type: CC BY 4.0

Affiliation: Korea Aerospace University

Abstract

In this paper, we propose a range-Doppler algorithm (RDA)-based synthetic aperture radar (SAR) processor for real-time SAR imaging and present FPGA-based implementation results. The processing steps for the RDA include range compression, range cell migration correction (RCMC), and azimuth compression. A matched filtering unit (MFU) and an RCMC processing unit (RPU) are required for real-time processing. Therefore, the proposed RDA-based SAR processor contains an MFU that uses the mixed-radix multi-path delay commutator (MRMDC) FFT and an RPU. The MFU reduces the memory requirements by applying a decimation-in-frequency (DIF) FFT and decimation-in-time (DIT) IFFT. The RPU provides a variable tap size and variable interpolation kernel. In addition, the MFU and RPU are designed to enable parallel processing of four 32-bit which are transferred via a 128-bit AXI bus. The proposed RDA-based SAR processor was designed using Verilog-HDL and implemented in a Xilinx UltraScale+ MPSoC FPGA device. After comparing the execution time taken by the proposed SAR processor with that taken by an ARM cortex-A53 microprocessor, we observed a 85-fold speedup for a 2048 × 2048 pixel image. A performance evaluation based on related studies indicated that the proposed processor achieved an execution time that was approximately 6.5 times less than those of previous FPGA implementations of RDA processors.

Highlights

A synthetic aperture radar (SAR) is an active sensor system that operates in the microwave band
We propose an range-Doppler algorithm (RDA)-based SAR processor containing a matched filtering unit (MFU) using a mixed-radix multi-path delay commutator (MRMDC) fast Fourier transform (FFT) processor and an range cell migration correction (RCMC) processing unit (RPU)
The MFU and RPU included in the proposed RDA-based SAR processor were designed using the Verilog hardware description language (HDL) and were implemented on a Xilinx Zynq Ultrascale+ field programmable gate arrays (FPGAs) device

Summary

Introduction

A synthetic aperture radar (SAR) is an active sensor system that operates in the microwave band. Hou et al used a Xilinx Virtex-6 FPGA to implement the RDA with a radix-2 single-butterfly FFT processor It acquired a 2048 × 4096 pixel image in 12.03 s at a speed of 200 MHz [18]. Hossain et al used a Xilinx Virtex-6 FPGA to implement the RDA with a radix-2 SDF FFT processor It acquired a 2048 × 900 pixel image in 2.08 s at a speed of 200 MHz [19]. SAR image generation is complete once azimuth-matched filtering is performed via multiplication by the azimuth reference signal in the azimuth frequency domain, followed by the azimuth IFFT. The frequency-domain azimuth reference signal can be obtained as a complex conjugate of the second phase term of Equation (10), where Ka is a function of R0.

Proposed Hardware Architecture

Implementation and Acceleration Results

Conclusions