FPGA Implementation of QR Decomposition Using MGS Algorithm

Abstract

FPGA implementation of MGS-QRD is presented in this paper. Mapping conventional QR triangular array of (2m 2+3m+1) cells onto a linear architecture of m+1 cells is employed to reduce the number of required QR processors. The architecture for MGS-QRD implementation is discussed, including the structure of a boundary cell (BC) and internal cell (IC). A divider in BC is modified as a Look-Up Table (LUT) and multiplier. The multiplier divided from the divider can be accomplished by sharing it with another multiplier to reduce the resource for BC implementation. Furthermore, the conventional complex multiplication in IC is also modified with three multipliers and four adders. The designed architecture based on discrete mapping of MGS-QRD is implemented to examine FPGA resource utilization. The implementation results show the FPGA performance and resource utilization of MGS-QRD.