Abstract
The paper focuses on the design and Field Programmable Gate Array (FPGA) implementation of embedded system for time based dual encryption scheme with Delay Compulsion Function (DCF) and also illustrates the application of DCF in time based cryptography. Further, the strength of the time based FPGA encryption algorithm with and without using DCF is analyzed using a Nios II processor. This proposed scheme enhances the security of vital data against Brute force attack by incorporating a temporal key distribution where two different keys encrypt the data simultaneously, one being the regular key and the other being the time. The time is included using a dynamically varying number of shifts thereby allowing the system to wait for the duration and this forms the second dimension of the key. Presently, available encryption systems suffer from Brute Force attack in which all the key combinations are tried in order to find the correct key. In such a case, the time taken for breaking the key depends on the speed of the system used for cryptanalysis. The proposed system adds complexity by using dynamically varying sequence of operations, by including the time as a second dimension of the key besides minimizing the possibility of Brute Force attack and increasing the time required for cryptanalysis irrespective of the system capability. As the proposed system needs concurrent execution and real time processing, the system is implemented using Altera Stratix II FPGA and the results are presented.
Highlights
Introduction to CryptographyCryptography has emerged as a fundamental building block of computer security and is the science of keepingHow to cite this paper: Prabakar, T.N., Lakshmi, B. and Seetharaman, G. (2016) Field Programmable Gate Array (FPGA) Implementation of Non-Linear Cryptography
Even though the software implementation of encryption algorithms has the advantages of portability, flexibility, and ease of use, it provides a limited physical security and agility compared to hardware implementations
Linear Feedback Shift Register (LFSR) based Pseudo random number generator output XORed with key with the seed dictated by the key itself can be used as a delay compulsion function
Summary
How to cite this paper: Prabakar, T.N., Lakshmi, B. and Seetharaman, G. (2016) FPGA Implementation of Non-Linear Cryptography. It protects information from unauthorized or accidental disclosure while the information is in transit or in storage, using two processes called encryption (data locking with the key) and decryption (data unlocking with the key). The encryption algorithms are effectively implemented both on software and hardware platforms. Even though the software implementation of encryption algorithms has the advantages of portability, flexibility, and ease of use, it provides a limited physical security and agility compared to hardware implementations. The implementation of software algorithms as hardware using FPGAs or Application Specific Integrated Circuits (ASICs) further reduces the time taken for cryptanalysis [1]
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