FPGA Implementation of Multilevel Space Vector PWM Algorithms

Abstract

Multilevel converters can meet the increasing demand of power rating and power quality associated with reduced harmonic distortion and lower electromagnetic interface. With the increase in number of levels, it is necessary to control more and more switches in parallel. Field programmable gate arrays (FPGAs), with their concurrent processing capability, are suitable for the implementation of multilevel modulation algorithms. Among them, space vector pulse width modulation algorithms offer great flexibility to optimise switching waveforms. In this paper the SVPWM technique is analysed and implemented in FPGA. The SVPWM pulses thus generated through the FPGA tool is given as switching pulses to the VSI circuit to trigger the three phase induction motor. FPGA is chosen due to its fast prototyping, simple hardware and software design. Simulation results are provided along with the theoretical analysis in terms of THD, output fundamental voltage and voltage transfer ratio to verify the feasibility of operation.