FPGA Implementation of MRMN with Step-Size Scaler Adaptive Filter for Impulsive Noise Reduction

Abstract

Noise reduction is an essential part of the signal processing for error-free analysis and critical measurements of the signal. Various robust mixed norm (RMN)-based adaptive algorithms have been reported to remove Gaussian and impulsive noise together. In this paper, a modified robust mixed norm (MRMN) with step-size scaler-based adaptive filter has been proposed to suppress the impulsive and Gaussian noise in system identification application. Further, an attempt has been made to develop an algorithm that simultaneously improves the rate of convergence and reduce the steady-state error (SSE). The proposed adaptive algorithm on an average decreases 13.2% SSE at the same initial rate of convergence, and at the same SSE, the rate of convergence is increased by 43.8% as compared to the existing mixed norm-based adaptive algorithms. Moreover, the hardware architecture of the proposed algorithm has been implemented using VHDL on various FPGA platforms. The proposed hardware implementation of the weight update block leads to high-speed realization of the adaptive filter with little increases in hardware resources. The architecture offers a maximum clock frequency of 66.53 MHz when implemented on Virtex 5 FPGA.