FPGA Implementation of Low-Latency Recursive Median Filter

Abstract

The recursive median filter has stronger noise at-tenuation capability than the median filter, especially for high-intensity and irregularly distributed noise. However, the recursive operation prevents recursive median filter from being pipelined, which leads to the recursive median filter being not real-time enough to be widely applied. This paper presents an FPGA implementation of low-latency recursive median filter. The proposed architecture completes the median calculation of the current window and the data pre-processing of the next window in one clock cycle, thereby reducing the calculation complexity of each median. The results show that for 5x5 window, the proposed recursive median filter core operates at a maximum frequency of 334 MHz on a zynq ultrascale+ FPGA device, which meets the real-time processing requirements for Full High Definition(FHD) images.