Abstract
According to the limitation of resources on satellite, this paper focuses on the design and realization of low complexity LDPC decoder. A new implementation method of LDPC decoder is proposed, a various kinds of LDPC codes could be supported. Finally, a (4096, 2048) LDPC decoder is implemented for verification based on a Xilinx Vertex4 xc4vsx35 FPGA platform. The implementation result shows that only 4% FPGA logic resources were consumed and the maximum clock frequency could achieve 180MHz.
Highlights
The low-density parity-check (LDPC) code was proposed by Gallager[1] in 1962
LDPC decoder design with low-complexity realization is the basis and prerequisite of LDPC code for satellite applications customized for the limited payload resources of the satellite
The results show that the hardware resource consumption of the LDPC decoder designed by the proposed method is obviously less than that of traditional serial and partial parallel decoders
Summary
The low-density parity-check (LDPC) code was proposed by Gallager[1] in 1962. Such codes are linear block codes with low density parity check matrix. The serial decoding structure presents low realization complexity but long decoding delay and low throughput. The full parallel structure exhibits low decoding delay, large throughput, and high complexity; it is difficult to achieve the hardware implementation. The partial parallel structure can achieve a good balance between realization complexity and decoding speed. A low-complexity FPGA realization structure is proposed for the two decoding algorithms. The design based on Xilinx xc4vsx chip is experimentally verified, and the results are compared with the traditional serial decoders and partial parallel decoders. The results show that the hardware resource consumption of the LDPC decoder designed by the proposed method is obviously less than that of traditional serial and partial parallel decoders. If HxT 0 holds or the maximum iteration number is reached, the decoding process ends; otherwise, the decoding continues from Step 2
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