Abstract
FPGA implementation of impedance‐compensated phase‐locked loop for HVDC converters
Highlights
In this chapter, the background and motivation of this research are discussed
Ajinai[8] investigated the dynamic performance of the IC-Phase-Locked Loop (PLL) in HVdc systems, the results show that the Impedance-Compensated Phase-Locked Loop (IC-PLL) has improved dynamic performance as compared with traditional approaches such as the Trans-vector PLL (TV-PLL)[9]
Case 3: FPGA-based IC-PLL is incorporated with the test circuit simulated inside the Real-Time Digital Simulator (RTDS)
Summary
The background and motivation of this research are discussed. The research objectives and the outline of the thesis are listed at the end of this chapter. The rapid increase in electrical power demand has accelerated the development of High Voltage direct current(HVdc) transmission technology. Electrical power was delivered from the generating station to the load through ac transmission lines. Ac transmission system has some limitations and disadvantages for long distance transmission, such as high transmission losses, lower power transfer capability and possible loss of synchronism when interconnecting two asynchronous networks [1]. The first commercial HVdc system, the Gotland HVdc link began to operate in Chapter 1: Introduction. Many HVdc systems were built around the world to deliver power over long distances. In Canada, there are many HVdc projects such as the Nelson River Bipole 1, Bipole 2 and Quebec-New England HVdc system[3]
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