FPGA Implementation of Hopfield Networks for Systems Identification

Abstract

This contribution presents the hardware implementation of a neural system, which is a variant of a Hopfield network, modified to perform parametric identification of dynamical systems, so that the resulting network possess time-varying weights. The implementation, which is accomplished on FPGA circuits, is carefully designed so that it is able to deal with these dynamic weights, as well as preserve the natural parallelism of neural networks, at a limited cost in terms of occupied area and processing time. The design achieves modularity and flexibility, due to the usage of parametric VHDL to describe the network. The functional simulation and the synthesis show the viability of the design, whose refinement will lead to the development of an embedded adaptive controller for autonomous systems.