FPGA Implementation of High Quality Random Number Generator Using LUT Based Shift Registers

Abstract

Random numbers are required for wide range of applications such as in encryption of data, testing and Monte-Carlo simulations. So, hardware implementation of random number generator is inevitable. FPGA Optimized RNGs are more efficient in terms of resource than software based RNGs. The LUT-SR RNG, a type of FPGA RNG in which LUTs are configured into shift registers with varying length. The existing work provides a midpoint between LUT-OPT RNG and LUT-FIFO RNG. In the enhancement work, we proposed modified LUT-SR RNG which provides more randomness, quality and minimum resource utilization than the existing LUT-SR generator. Inorder to improve the randomness quadratic residue method is employed. Linear Congruential Generator (LCG) algorithm, one of the oldest and well known algorithm is also used in modified LUT-SR RNG to enhance the performance. Here design was made by VHDL programming language by using Xilinx software.