FPGA Implementation of High-Performance s-box Model and Bit-level Masking for AES Cryptosystem

Abstract

The inadequacies inherent in the existing cryptosystem have driven the development of exploit the benefits of cipher key characteristics and associated key generation tasks in cryptosystems for high-performance security systems. In this paper, cipher key-related issues that exists in conventional symmetric AES crypto system is considered as predominant issues and also discussed other problems such as lack of throughput rate, reliability and unified key management problems are considered and solved using appropriate hierarchical transformation measures. The inner stage pipelining is introduced over composite field based s-box transformation models to reduce the path delay. In addition to that, this work also includes some bit level masking technique for AES. The improved diffusion and confusion metrics of bit masking transformation model mitigates key management related issues. An extensive analysis of data rate proved the performance metrics of proposed AES model. And finally, FPGA implementation is carried out to validate the performance metrics in real time.