FPGA implementation of GF (P/sup m/) exponentiation for digital signature and authentication scheme

Abstract

This contribution describes a field programmable gate array (FPGA) implementation of exponentiation over GF (P/sup m/), the arithmetic architecture of which is based on the Fermat number-transform (FNT). The main applications of the processor are digital signature and authentication schemes. It is then shown how, by decomposing a high degree polynomial into several lower degree polynomials to execute multiplication, the area is minimized while the throughput is maximized. The processor consists of special operational blocks for FNT, IFNT, point multiplier, and modular operation. An Xc2v1000-4fg256 (Xilinx Virtex2 series FPGA, 100 million gates) is used to accomplish the computation, and the FPGA implementation result is provided and evaluated. It is shown that it takes 65 /spl mu/s to accomplish one computation.