FPGA implementation of fast serial 64-points FFT/IFFT block without reordering block

Abstract

There has been many FPGA implementation of serial Fast Fourier Transform (FFT) operation. In the most cases, output of the serial FFT block is in bit-reversed order, so it needs a reordering block to reorder the output. However, some of FFT applications do not require ordered output of FFT, such like Spectral Subtraction method. In this paper, we propose an FPGA implementation of serial FFT and IFFT architecture in one block without reordering block. By not implementing the reordering block, we can save some clock cycles latency and increase speed of the block. The architecture is implemented in Altera DE2-70 board with Cyclone II EP2C35F672C6 FPGA chip. Our 64-points FFT/IFFT block utilizes 2960 logic elements or half of logic elements utilized by Altera MegaFunction's FFT IP. The block can work in maximum frequency of 84.55MHz and perform 64-points FFT/IFFT operation in 863.4ns.