FPGA IMPLEMENTATION OF ERROR DETECTION AND CORRECTION IN SRAM EMULATED TCAMS

Abstract

Ternary content-addressable memory (TCAM) is often used to categorize packets in network devices Packet forwarding, software- define networking, and security are just a few of the applications for this technology. TCAMs may be implemented in networking Applications- specific integrated circuits (ASICs) either as a stand -alone device or as an intellectual property (IP) unit. TCAM block may be added to FPGAs, despite the fact that they don't come pre-configured. For SDN applications, FPGAs were an excellent solution because of their versatility, and most FPGA suppliers provide SDN development kits. The logic blocks of FPGA must be emulated as TCAMs in order to implement TCAM capabilities. Modern FPGAs include a plethora of memory blocks that may be used to construct TCAMs, which some of these systems may take use of. Because mild mistakes may lead to data loss, this is undesirable. It is possible to remedy faults by using error correction methods such as a parity check, although this increases the overall memory capacity by a single bit per word. Here, Major concern is with safeguarding the memory utilized to simulate TCAMs. As only a subset of the potential memory content is authentic, a parity bit may be utilized to repair most single-bit mistake. In this project, a novel methodology implemented to safeguard memory utilizing for simulating TCAMs using parity check, Block Parity and Hamming code techniques. The Proposed algorithm designed, verified using Xilinx Vivado tool and implemented on Xilinx Nexsys DDR Based ARTIX-7 FPGA.