FPGA implementation of error control codes in VHDL: An undergraduate research project

Abstract

AbstractError control codes (ECC) play an important role in the detection and correction of data errors over unreliable or noisy communication channels. The main idea of ECC is to add redundant bits to the message on the transmitter, which can be used to detect and correct certain errors on the receiver. ECC are used in numerous applications such as telecommunications, Internet, and data storage. Different types of ECC exist such as linear block, convolutional, and turbo codes. This paper presents results from an innovative undergraduate research project involving implementation of linear block, cyclic and convolutional codes in very high speed integrated circuit hardware description language (VHDL) using a field‐programmable gate array (FPGA). FPGA is a suitable platform for implementing ECC due to the advantages of performance, time to market, cost, reliability, and long‐term maintenance. As part of this project, (7,4) Hamming code used for linear block and cyclic codes and convolutional codes with constraint length k of 3 and code rate (k/n) of 1/2 were implemented in VHDL on a Xilinx Spartan‐6 FPGA using ISE 14.7. Two undergraduate students at Purdue University Northwest worked on this project. This was the students’ first exposure to ECC, VHDL, and FPGA, as undergraduate students are usually not introduced to these topics in traditional electrical and computer engineering curriculum. The goal of this project was to provide students with hands‐on experience using industry‐standard VHDL software and FPGA hardware platforms to implement ECC. This paper presents the results of this innovative project including register‐transfer level schematics, simulations, and VHDL code for encoders and decoders for the various ECC implemented, and students’ reflections on the project.