FPGA implementation of digital upconversion using distributed arithmetic FIR filters

Abstract

Distributed arithmetic (DA) is a high speed multiplication technique used for implementation of digital filters and signal upconversions. The DA is bit serial word parallel approach where throughput rate does not depend on filter length or data size. In this work a serial DA method is employed for FPGA implementation of digital component of the TIGER transmitter. A prototype has been synthesized and mapped using Xilinx Virtex II. The design with fourteen bit 100 tap FIR filter and upsampling ratio of eight takes only 18% of the device. Performance of the DA modulator is discussed with variable filter length and precision level.