Abstract
“ADS-B Messages” transmitted on 1090MHz are the Mode S Extended Squitters. When a Mode A/C fruit interferes with a mode S Extended Squitter, some of ADS-B signals may be received in error. These errors need to be corrected by some correction methods. To solve this problem, an error detection and correction algorithm using cyclic redundancy check (CRC) based on bit and confidence declaration is proposed in this paper. Then, the proposed algorithm using the Verilog hardware description language is verified by MODELSIM joint ISE simulation and realized on Field Programmable Gate Array (FPGA) based on ADS-B system. The results show that the algorithm can effective detect and correct data transmission error, which effective advances the reliability of the signal transmission for ADS-B system.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
