FPGA Implementation of an Approximate Booth-Wallace Tree Multiplier

Abstract

Multiplier is a basic building block of a digital processor. Approximate computing has emerged as a new paradigm for energy-efficient design of circuits and systems. In this paper, we have proposed an approximate signed Booth wallace multiplier. The proposed multiplier is designed using an approximate modified booth algorithm, an approximate 4:2 compressor, approximate full adder and half adder cells and an approximate wallace tree structure. The results show that there is a decrease in power consumption and delay by 3.9% and 16.7% respectively. The multiplier is designed using Verilog HDL using Vivado 2017.4. The FPGA implementation is done targeting the FPGA board which is equipped with Xilinx Artix-7 FPGA.